CVE-2025-50897

Description

A vulnerability exists in riscv-boom SonicBOOM 1.2 (BOOMv1.2) processor implementation, where valid virtual-to-physical address translations configured with write permissions (PTE_W) in SV39 mode may incorrectly trigger a Store/AMO access fault during store instructions (sd). This occurs despite the presence of proper page table entries and valid memory access modes. The fault is reproducible when transitioning into virtual memory and attempting store operations in mapped kernel memory, indicating a potential flaw in the MMU, PMP, or memory access enforcement logic. This may cause unexpected kernel panics or denial of service in systems using BOOMv1.2.

References

https://github.com/riscv-software-src/riscv-isa-sim

https://github.com/riscv-boom/riscv-boom

https://github.com/LuLuji04/POC-Boomv1.2

Details

Source: Mitre, NVD

Risk Information

CVSS v2

CVSS v3

EPSS